Processes and memories that are produced and used at the present time usually operate in binary logic. The logic states “0” and “1” thereby prescribed are in each case allocated a charge or voltage state in the corresponding electrically operated circuit arrangements.
Dynamic random access memory cells (so-called DRAM cells) comprise a selection transistor and a storage capacitor. In order to define a charge state in the storage capacitor, a voltage of 0.9 V may be applied for example to the counterelectrode—this is a doped buried well in the case where trench capacitors are used. The two charge states can then be achieved by the storage node being brought to a voltage potential of either 0 V or to 1.8 V.
Dynamic memories have the property that they have to be reloaded again at regular intervals, which is referred to as a so-called refresh. This is due to leakage currents which result in any charge stored in the capacitor gradually flowing away. In order to carry out a refresh, the charge information is read from a memory cell by means of the selection transistor and compared with a reference charge or voltage value, e.g., by means of an amplifier unit. The reference value serves as a limit between the charge or voltage value range corresponding to the logic state “1”, or that corresponding to the logic state “0”.
Ideally, the voltage state of a cell is at a voltage value, for example 0V or 1.8 V, allocated to it during a charge writing process. Due to the above-mentioned leakage currents, in time these written voltage values strive toward an equilibrium state, which may be about 0.9 V in this example. During the read-out process there is the added factor that the bit line voltage decreases from 1.8 V to 1.2 V, for example, depending on the coupling ratio between bit line and capacitor. In the event that there is still sufficient distance between such an adapting voltage value and the reference value of 0.9 V, set at the equilibrium state, by means of the amplifier unit, it is possible, during the refresh process, for the value of 1.2 V to be assigned to the upper voltage range of the logic state “1” and for the ideal value 1.8 V to be written again to the storage capacitor via the selection transistor by means of the amplifier unit.
However, the situation often arises wherein a memory cell is defective, so that a charge or voltage state can no longer be written to the memory cell. Therefore, during read-out, a voltage value near the equilibrium state is typically output, which value thus also lies near the reference value for the voltage. Since either one voltage state or the other must be rewritten by the amplifier units used heretofore for the refresh, an erroneous refresh can occur. Since a read-out process is generally coupled to a refresh process, a charge state that was not actually originally stored can be simulated for the read-out in this case.
Such error handling is usually realized by means of additional check bits in the memory area. By way of example, a parity bit may be stored in a memory cell required for this purpose, the parity bit being produced logically from the information of a cell sequence connected to a bit line. One disadvantage here is that a non-negligible outlay for calculation and verification of the check bits has to be expended both spatially and temporally.
The document JP 10-233092 A (and corresponding U.S. Pat. No. 5,696,725) discloses a sense amplifier in which the threshold voltage of n-MOS amplifier transistors can be changed by varying the bulk voltage.